Description:This patent relates to a method and apparatus for performing arithmetic operations and, more specifically, to digital adder and multiplier circuits.
Abstract:A method and apparatus for n-bit by n-bit multiplication is disclosed using paralleled 4-bit by 4-bit multipliers and cascaded adder structures. The cascaded adder structures may be used to produce non-pipelined, integer, n-bit by n-bit multipliers with higher throughput than systolic array multipliers of similar geometries.
Issue Date: 06/15/1999
Application Date: 09/12/1996
Post Date: 03/02/2018
UTEP Docket No: 2000-087
